Notes: Hall D F1 chip prototyping

[Elton Smith <elton@jlab.org>]

Notes: F1 chip prototyping / Wed Sep 29
Present: Chris Cuevas, Fernando Barbosa, Ed Jastrzembski, Dave Abbott,
Elton Smith

We discussed various issues related to what we wish to learn with the F1
prototyping activities.

Elton passed out some information about the packaging of the F1 chip for
COMPASS (esp. the CATCHX board).

Communication/data transfer rates drives several design considerations.
It is desirable to package the F1 chips onto boards which fit in
standard crates. COMPASS has front-end boards which sit on the detector
and communicate to the CATCHX boards via 400 MHz hot-links. 

It is desirable for Hall D to have the flash ADCs and F1 TDCs be packaged
into similar form factors. Once signals get discriminated for the TDCs,
cable length is not a primary concern. Cable lengths for analog signals
into the ADCs certainly need to be minimized, so these will most likely
limit the distance from the detector to front-end crates. 

Packaging
   - VEPA crates do not seem like they are catching on
     - Not clear one should design around this standard  
   - 64X expected to be popular
     - Lack features we require: e.g. block reads
     - Noise isolation is a concern / proper power supplies my help
     - Possible Solutions: 
        - develop "custom" protocol for chain block transfer
        - build boards with capability to take over as masters
        - Specify low noise power supplies for crate

Prototyping suggestion
   - Use 64X standard
   - Build board which can be programmed as masters

Buy crate for prototyping soon. Get prices/order at next week's conference
   - Dave Abbott will pursue this
   - Full crate might be required for use with clean power supply.

Schedule
   - Fernando and Ed will work together
   - They will propose a schedule for producing a prototype based on their
     own availability and prototype concept. 


Please send comments to these notes, Elton.



Elton Smith
Jefferson Lab
elton@jlab.org
(757) 269-7625