Notes from Meeting with CAEN/Wiener Mon Apr 23

[Elton Smith <elton@jlab.org>]

I am passing on some of the notes I took during our conversations with
CAEN/Wiener representatives this afternoon. Others, please comment or add
to them.

Present: Ed Jastrzembski, Elton Smith, Elliott Wolin, Fernando Barbosa,
Vardan Gyurjyan, Dave Abbott, Fabrizio Catarsi, Andreas Ruben, HV designer
(missed his name).


Notes from Meeting with CAEN/Wiener Mon Apr 23
==============================================

V 890 pipeline TDC board (next generation of the V 767
------------------------------------------------------

LHC will use the chip that goes into this board directly on the detector.
Chip design is rad hard for this reason. CAEN is integrating the chips
into the V 890 board so that LHC experiments can test functionality of
electronics during beam tests beginning in summer of 2002.

Design calls for 32 channels per chip. According to preliminary design
sheet, it can work in either low resol (781 ps least count), med resol
(195 ps) or high resol (98 ps), corresponding to clock times of 40, 160 or
320 MHz clocks generated internally from a 40 MHz external signal.

This summer CAEN and CERN will solidify agreement for the number of chips
to be produced during a single production run. Estimated cost is 0.60
Swiss Francs/channel ==> approximately $15/chip. These are very
preliminary estimates as negotiations are under way.

F1 Chip
-------

CAEN has an agreement with ACAM to include the F1 chip in board designs.
However, current interest in the community has been pushing the V890
series.


Backplane discussions
---------------------

CAEN produces VME in at least three flavors to suit customers: a) CERN VME
(with middle connector) b) 32-bit 3-row J1/J2 connectors c) 64X 5-row
connectors. However, the 64X does not presently support two edge
transfers.

CPCI - CERN is not using this backplane except for tests. Most common
backplane is the CERN VME and some 64X.

The only experience in physics (relatively large scale) is the Auger DAQ
system. A group at Karlsruhe is developing their own boards.

Claim is that the market for industry is roughly equally divided between
VME and CPCI. No requests they are aware of from the physics community.

Fermilab, which in the past has been a major user of stardard crates is
now shifting its electronics closer to the detector and eliminating the
crate paradigm.

LHC has electronics spread out over the entire detector. Many discussions
of backplanes (e.g. CPCI and others) have been in progress for many years
without many clear outcomes.

Struck and Acquiris FADCs
-------------------------

They are aware of these products, but recommended getting details on the
product from the Struck web site (http://www.struck.de/)

Location of Electronics
-----------------------

Cost of crate system near detector is approximately equal to crate system
20-30 m away. (For example, the cost of connectors does not change). The
big difference is between electronics directly on the detector compared to
electronics in crates.

Issues to be considered are: power dissipation, radiation hardness
(critical issue for LHC experiments).

Jefferson Lab F1 TDC Module
---------------------------

Ed handed out a description of the Jlab F1 TDC module. (Ed: Can we make
this available on
http://www.jlab.org/Hall-D/electronics/electronics.html?). This can be
used as a description of features which we would like to incorporate into
a TDC board design. CAEN will evaluate it to determine how difficult it
would be for them to incorporate these features into one of their TDC
boards.









-- 
Elton Smith
Jefferson Lab
elton@jlab.org
(757) 269-7625