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F1TDC (fwd)




I am passing on the summary by Fernando, with some anotations of my own:

Added Note: Ed raised the question as to whether there are timing shifts
in the chips with more than one channel per chip. We have seen this
behavior in early discriminators (see TOF paper page 283). This should be
checked for chips to be used.

Item Number 4: I thought we agreed to route lines to an FPGA and a
connector to pull signals off the board. Allow for an FPGA which is
thought to be large enough to implement the interface, as it is not yet
programmed. Ed would decide the actual FPGA size to be used.


Added Note from Ed:

- Ed raised the question as to whether this prototype as a replacement for
existing modules should be made to operate in common stop mode. We need to
revisit this issue at the next meeting, as there was discussion, but no
resolution.

- There was a short discussion about how to route common signals to the
TDC boards. Ed suggested that regardless of which standard is used (e.g.
VME, Compact PCI, etc) that we require that the hardware allow for proper
routing, even if it requires some custom specification.

- Next meeting: Wed Aug 9 9:00.  See you then.



---------- Forwarded message ----------
Date: Wed, 11 Jul 2001 17:25:21 -0400
From: Fernando J. Barbosa <barbosa@jlab.org>
To: Elton Smith <elton@jlab.org>
Subject: F1TDC

Hi, Elton. Here is a summary for the F1TDC prototype specifications, as we
discussed at our meeting this morning.

    The first F1TDC prototype is intended to test and characterize the
hardware capabilities of the F1 chips and all of the ancillary circuitry
in a format as close as possible to the real TDC. For such, the backend
circuitry from the F1 data bus to the VME backplane will be replaced with
a simple VME interface that enables reading the data, status and
programming the F1 chips via a serial link, all implemented on a FPGA or
similar device.

        1.  64 low-res/32 hi-res channels, 6U VME form factor - The layout
will be close to the final version and will enable testing the module with
the power supplies/filtering/conversion for noise levels and other
parameters in real operation.

        2.  ECL pull down/terminations will be divided into to tests
            - 2 connectors (32 low-res channels) will have inputs pulled
                down to -2V through 50 Ohm from each of the differential
                lines
             - 2 connectors will have inputs terminated into 100 Ohm
                across the diff lines.

            Although I favor the first approach, there are some concerns
that ground loops caused by different power supplies used for the pull
downs at the receiver (F1TDC) and the driver (any ECL driving circuitry,
i.e., discriminators) may cause some unstable conditions. This concern is
real if one is to use unbalanced drivers and/or receivers. Anyway, this
will be tested.

        3.  There will be no attempt to equalize channel delays for a
"zero" skew TDC as cables and the rest of the system will introduce skews.
Calibration will provide the correct skew values for all channels.

        4.  VME interface to be determined. Is VME64X required at this
stage? I believe we just need something really simple that doesn't require
a lot of resources.

        5.  I hope we can agree on some plan of action so that I can start
testing the prototype sometime in September. I have talked to Ed and
James, and as suggested by Chris, regarding the VME interface. Hopefully,
we will have a better understanding of the tasks at hand by next meeting.

        6.  Testing of the prototype will also require some resources and
James is willing to help. Additional test instrumentation will be required
(i.e., purchased) to fully characterize the TDCs.

    I am sure there will be some additional questions before the prototype
is implemented. Please, feel free to add any comments.

    Best regards,
        Fernando
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