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Fw: just a question: (fwd)





---------- Forwarded message ----------
Date: Thu, 17 Jan 2002 16:10:20 -0500
From: Andi Klein <klein@physics.odu.edu>
To: barbosa@jlab.org, ptsmith@indiana.edu
Cc: elton@jlab.org
Subject: Fw: just a question:

Dear Paul and Fernando
What follows is part of a message I got from Alan Bross at FNAL, concerning
some work
D0 is planning to do. Now I am an absolute idiot when it comes (among other
things) to electronics. So I thought I forward this to the experts, to see
if you guys would be interested/ if this might be interesting for the VLPCs
in our case. Some more thought about the VLPCS and fibers started to
convince me that we might have a chance to get somewhere around 1-1.5 nsec
timing resolution out of the system, so I think we need to have TDC read out
of the VLPC's
Cheers, Andi

From A. Bross

D0 is also working on a new front-end chip  (see attached).  With a
modification, it might be possible to develop a chip that could drive
something like the ATLAS
TDC chip (http://www-atlas.kek.jp/tdc/).  I have briefly discussed this with
one of our chip designers.  It might be possible!  It would yield a VLPC
front end board (512 ch) with discriminator, TDC, and analog output.  This
would involve a new chip and significant cost, however.  This is not
something D0 is going to do unless
we can show that timing information can help triggering  (maybe?).  Even if
it does, the $$ are probably not there.  I will take this up with the chip
designer a bit, but
I do not think that it will go very far very fast.  Just an
idea/possibility.

If you guys have some resources to put to this, some progress can be made.
There are very limited resources available at Fermilab for this at this
time.

Regards,

Alan




SIFT TDR 20011002.doc