VME 320 readout controller (fwd)

[Elton Smith <elton@jlab.org>]

---------- Forwarded message ----------
Date: Thu, 28 Feb 2002 18:03:31 +0100
From: Matthias Kirsch <matthias.kirsch@wtnet.de>
Reply-To: Matthias Kirsch <mki@struck.de>
To: David Abbott <abbottd@jlab.org>
Cc: elton@jlab.org, barbosa@jlab.org
Subject: VME 320 readout controller

Hi David,
I think I had informed you about the 90 MBytes/s
between the SIS3300 FADC board and the SIS3100 VME
sequencer with 2eVME?
As you can imagine we are always looking which direction to
go into. Probably you guys are following up on the RTC magazine
also. This week my attraction was directed to the announcement
of Motorolas Tempe Chip and TIs V320 driver chips. A contact
with SAIT (Samsung Insitute of Technology) pointed us into the
direction of the 5e network processor as possible future VME sequencer
interfacing chip. I could imagine, that the Tempe in conjunction with the
5e and one or two FPGAs will give a state of the art VME320 controller.
The main advantage of the new technology will be the fact, that no special
backplane will be needed with the TI chips (in contrast to the current
V320 technology). Interfacing to the controller will be possible via
standard Ethernet of the various speed grades.
Did you have a chance to work with the FADC boards yet?
Best regards
Matthias

ps.: I would prefer this message not to be inlcuded into the hall-D archive,
as the idea is in a very early stage.