Re: More on FDC

[Howard Fenker <hcf@jlab.org>]

Please see my remarks within the following...
	Howard

Elliott Wolin wrote:

> On gaps:
> 
> The trace and space definitions are dependent on manufacturing variables...

Just as an historical remark: after we simulated the chambers at SSC
we decided upon 0.25mm gap size.

> (Fernando and I know of no fundamental lower limit to the inter-cathode 
> gap size...anyone know of any?).
> 


I do, and I mentioned it at our meeting: narrower gap ==> higher inter-strip
capacitance ==> higher channel-channel crosstalk. You can only tolerate
so much.

*** Mehmet needs someone to work on electronic simulation for him!! ***


> 
> Picture frame pc board rigidity:
> 
> The anode wire pc board will likely need to be attached (glued, pinned, 
...

Often one finds that if the pc board is pinned flat (as it would
be when the chamber is assembled) this constrains the pc board sufficiently
to maintain the wire tension. While the pc board is usually thin,
the width of the board can be a significant source of rigidity.
I have a model for window frame stiffness from an engineer at
Fermilab. JLab engineers can also check this.

> 
> Gain sensitivity and tolerances:
> 
> Since we are using analog readouts we may be sensitive to gain 
> variations.  The gain sensitivity to the wire/cathode distance should be 
> calculated (standard formulas, I believe).

Typically the gain variation pales in comparison to Landau fluctuations,
and we cannot get rid of those. Gain variations/fluctuations have more
impact on the TDC information than on the strip interpolation, since
interpolation is based on charge ratios only, while the TDC sees threshold
crossings.