Two basic types of digitizing electronics will be used in \hd, \adc s and \tdc s.
Channels which measure energy will be continuously sampled with flash \adc s.
These boards would be designed by our collaboration;
 a conceptual design is shown in Fig.~\ref{fig:daq_fadc}.
\begin{figure}
  \centerline{\epsfig{file=ch8_fadc.eps,height=1.75in,width=5.25in}}
  \caption{Block diagram of \fadc\ board.}
  \label{fig:daq_fadc}
\end{figure} A dual-port RAM
running at the full \fadc\ speed 
continuosly stores the \fadc\ data.
The level 1 trigger signal
will copy data from the time window of interest to an output queue. A prototype of this board is currently being designed.  The general philosophy is to use commercial \fadc\ integrated
 circuits and programmable gate arrays.
Suitable \fadc\ ICs are being developed by industry for fully digital radio receivers.  An 8 bit, 200 MHz \fadc\ IC is available today for \~\$20 each.  Programmable gate arrays with internal dual-port RAM are also available today for \~\$20 each.  These ICs are used in high speed computer network routers.

Channels which require precise time measurements will use a multi-hit \tdc.
We are evaluating a few sources of such boards.
One company,
``Acam Messelectronic Gmbh''\footnote{see www.acam.de for details on the
``F1''},
has a prototype board based on the ``F1'' ASIC developed for the COMPASS
experiment at CERN. This design can provide up to 60\pstunit\ resolution and
is designed for high rate, low deadtime experiments.
 The \tdc s can store hits for several
microseconds
and are equipped with a filter and a muliple level buffering scheme so that only times from a region of interest are
read-out
