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Notes Phone Conference Nov 16




Notes Phone Conference Nov 16
-----------------------------
Participants: Gerard, Jim, Lars, Jan, Alex, Elton, Dan, Simon, Chris

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Topics

o Review of schedule for Drift Chamber Review
Elton gave a brief summary of the schedule. The drift chamber review,
although not yet scheduled, is expected for the end of February. Dan
indicated that it would be desirable to have tested some of the new
preamps based on the ASIC, as well as the new post-amp design from Gerard.
In addition the CD-2 review is expected for mid June 2007 and requires as
input reliable costs, schedules and nominal completion of 35% design.

o Update from Gerard on post-amp board
- The  design for the post-amp prototype is close to completion. A final
update on the off-set level shift circuitry is needed. The layout is 99%
complete. The prototype will be compatible both with the standard 34-pin
connector and a new mini-D 50-pin connector which could service 24
channels. The board is a VME board with 16 lemo connector outputs which
can be used as inputs to the current commercial fADCs in use. He expects
to be able to send the board out for fabrication (10 boards) next week.
- The shaper boards should be available in mid december. Gerard will stuff
one board at IUCF and keep for testing. A few boards will be sent to JLab
and Chris has manpower that can stuff additional boards as needed to make
them available to Simon for testing on the FDC prototype.

o Update from Gerard on DC FADC
- The goal is to have the design advanced sufficiently by Feb/Mar to
provide good estimates for cost and schedule.
- The design should be completed by May so that prototype boards can be
sent out for fabrication.

o Update from Mitch on ASIC development
www.hep.upenn.edu/HEP_INST/INST_Projects/GLUeX/Design_Status/Nov_16_TSMC_Implentation/
- Payments: Alberta has sumitted payments to UPenn and, although they are
still being processed by the finance offices, Mitch does have
authorization to charge against the account.
- The slides provide an update on the progress to date. The adaptation to
the TSMC 0.25 micron RF process is expected by Dec 6. The layout still
needs to be prepared before the design is submitted. A TSMC run is planned
for Feb 12 and this would be the target for producing the first batch of
ASICs. Typical turn around times are 15 weeks, but schedules need to be
checked for TSMC process.
- Hand-wired boards will be used at UPenn to test the first chips for
basic operation.
- Alberta will perform electronic tests of the chips likely using the
boards that can be mounted on the drift chamber. They can look for cross
talk and check higher level performance of the chips.
- After these basic bench tests, preamp boards can be made available for
testing on the FDC prototype itself.
- Dan mentioned that once the preamp boards are available, it will take
them at least two weeks to evaluate them.
- Chris mentioned that as soon as the pin-out is known, they can start
laying out the board. The final chip design is not required. Once the
connectors are specified, cooling and other design issues can be started
in parallel.

o Status of other projects and electronics coordinator
- Elton, Chris and Jim have circulated a draft statement-of-work for Lars
and Jan to start spending dedicated time on the Hall D electronics,
especially coordinating the overall effort. There is a tentative agreement
with the department at Alberta to allow Lars to spend half time on this
project over the next six months, with a longer period to be negociated.


Elton Smith
Jefferson Lab
elton@jlab.org
(757) 269-7625