Re: Tracking fADC

[Gerard Visser <gvisser@indiana.edu>]

Hi Chris,
	After further delays mostly due to other projects, I can now finally 
say the boards went to fab on 12/4. I expect to receive them on 12/15 
(elected 7 working day turnaround).
	I will quickly evaluate one board here and send on to you several bare 
boards and parts. [And documentation, of course. I am finalizing that 
now.] Can you remind me, how many total Struck ADC's do we have? I seem 
to remember 5 200 MHz and 1 100 MHz, but maybe I remember wrong... 
Please check/clarify. If we have 6 Struck boards that is 6*8 channels so 
I would propose to assemble 4 or 5 of the 16 channel amp/shaper boards. 
No point to committing parts to more boards than we have ADC's to read, 
although I am procuring parts for 8 amp/shaper boards per our MOU. Your 
tech will be assembling by hand, right? [There are no leadless or 
bottom-soldered parts on this board.]
	I can come to JLab in January to work with Simon to set up the 
amp/shaper boards and make measurements. I may have to travel to BNL for 
STAR setup activities, schedule depends on RHIC run schedule which is in 
flux still. We'll have to work around this, sorry.
	Pending a decision to use 24-channel (as opposed to 16-channel) 
granularity on the cables and the preamp boards, the tracking ADC module 
will be 72 channels rather than 64. This would be still on a 6U VME 
module (36 channels on main board and 36 more on a mezzanine). If I 
understand right, Dan & Simon and Fernando all basically agree to the 
24-channel granularity.
	I don't think it makes much sense to have two different slow ADC's (65 
& 125). We should settle on one sample rate. _If_ it turns out then that 
we use a part which is available also in a pin and functional compatible 
lower speed version, then we could consider saving some money this way. 
I think the costing should assume not doing this, at this point.
	The sample rate of the prototype ADC is not yet finalized. Based on 
request from Curtis it should be >100 MHz; as you note, that's what the 
detector electronics summary table shows too. I'll need to investigate 
the current market offerings and pick a sample rate not less than 100 
MHz, based on the best that can be done today for maximum board density 
and minimum power. I suspect also this exercise will show that 
significant cost (and power ...--> cost again) savings are possible at 
some lower sample rates like 80 MHz. That was the case when I looked at 
this last, but it has been a while. I need time to look at the latest parts.
	Is the ADC board cost information needed by February per our Nov 16th 
phone conference, or much sooner?
	Talk to you later,

	Gerard

C. Cuevas wrote:
> Hi Gerard,
> 
> A quick message to ask you about the amplifier/shaper boards and to also 
> ask you about the flash ADC design.
> 
> We can begin assembly as soon as you send the amp/shaper board.  Please 
> include any detailed drawings needed for SMD reference designators etc.  
> Presumably you will also send a bill of materials with the 'kit'.
> 
> I am tasked with reviewing the cost/schedule for the Hall D project in 
> preparations for a review.  The GlueX detector 'table' shows a 12 bit 
> 100Mhz design for the FDC and CDC.  I know you are designing the 64 
> channel fADC, but what is the sample rate for the prototype unit? 
> 65Msps? I have included the detector 'table' and know that there will be 
> two flash ADC boards.  Some of the cost spreadsheets I am reviewing show 
> a 65Msps and 125Msps board so I will sort that out with Elton.
> Please reply or call at your earliest convenience,
> 
> Chris
> (757)269-5053
> ~~~~~~~~~~~~~~~~
>