Re: receiver/shaper board measurements

[Gerard Visser <gvisser@indiana.edu>]

Hi Simon,
	I'll check with Matthias to be sure I have the most recent revision of 
the manual, but the way I read it, the external sample clock may go up 
to 210 MHz but the internal clock (as you are using) _is_ 200 MHz. So 
your time bins are definitely 5ns. [By the way, this is then a possible 
source of error in correlating the timing from ADC to timing from the 
F1TDC... If you use the wrong sample rate factor in the analysis you 
must get a worse timing comparison, no? Something to think about.]
	I'm having a hard time reconciling the peaking time of the pulse as 
seen on the scope, which is clearly about 25ns [in agreement with my 
measurements here and the design value, 23ns], versus that seen in the 
one pulse you show captured by the ADC, about 9 ticks, which is 45ns at 
a sample rate of 200 MHz. _Perhaps_ it was just that this particular 
pulse consisted of two clusters about 20ns apart (I see some like that 
on the 2nd scope picture). Can you post a couple more ADC captures? [It 
would also be good to see whether the wacky ringing after the pulse is 
present in all the pulses.]
	Is there any chance you can procure some twist-n-flat cables (as 
described in my earlier message) prior to my visit? It is possible that 
it won't behave differently, but it is also quite possible that it could 
make a significant improvement. It would really be nice to try it out.
	If there's time, try out ch8 (and/or other channel) with the cathodes 
to get some idea of pulse height for me before I stuff the second board 
with the gain resistors.
	Thanks for all your work on this, see you soon,

	Gerard


Simon Taylor wrote:
> Hi, Gerard.
> 
> The flash-ADC data shown is not for channel 8. The high voltage settings
> are +1650V/-300V as before.  The cable is not twisted pair cable but
> between flat portions each wire seems to be jumbled up randomly within the
> jacket.  The SIS3320 is running off its internal clock at the maximum
> sampling rate.  It's not clear to me whether this is 210 MHz or 200 MHz;
> I've seen both numbers in the manual.  The next lowest (internal) clock
> setting is 100 MHz.
> 
> Simon
> 

>