Re: VME64x Pinout for F1TDC, fADC125, fADC250

["Fernando J. Barbosa" <barbosa@jlab.org>]

Hi Chris,

    Thanks for the comments.

    The document outlines all the connections and signal levels and 
provides an overview of the elements of a VXS system. I completely agree 
that a VXS transition card scheme does not make any sense for our 
applications as it would be similar to a hub implementation, anyway.

    The document is also forward looking in that it is a recommendation 
or endorsement for future work. It is understood that the hub was a 
solution for the early F1TDC system when VXS was not available and it 
should be maintained for legacy systems.

    The pin allocation and labeling is subject to change as the design 
evolves to a more finalized state. Additionally, and to avoid any 
confusion in the future, I strongly recommend that we label the P0 
connector pins as per VITA 41 and as to be as generic as possible. For 
instance, instead of assigning a lane to be CLOCK, it should be labeled 
DP2+ and DP2- (Differential Pair #). In this manner, the lane function 
is dependent on its end-use (payload card) and could have completely 
different functions depending on the switch and payload card 
combination. This is the great advantage of the VXS implementation.

    I will update the file as needed. I also favor an electronics forum 
during the Hall D collaboration with the emphasis on discussions with 
minor topical presentations. It is my hope that documentation like this 
will generate enough interest before that meeting.

Regards,
Fernando





C. Cuevas wrote:
> Hi,
>
> The document is very useful and even though it may seem like 
> duplicated effort, I have attached two spreadsheets.  The first is 
> simply a consolidated one page view of P1 & P2 assignments for the 
> FADC-250, F1TDC, and FADC-125.  The second is a proposed 21 slot VXS 
> backplane map that has been sent to VXS crate enclosure companies for 
> budget estimates.  As you may all know, we have been performing all 
> prototype testing with 12 slot VXS crates and the payload port to 
> physical slot map must be defined for the full crate systems this year.
>
> I have omitted the FADC-250 P0 connection definitions, because we will 
> have to re-assign these pins after we have results from the prototype 
> R&D activities that include the flash and the energy sum 'collector' 
> board.
> We definitely do not want to implement a VXS transition card scheme, 
> because that implies even more distribution hardware.  I am waiting to 
> receive the budgetary estimate for the 21 slot backplane (crate and 
> power supply included) so that a concise cost comparison can be 
> performed.  I strongly agree with the VXS signal distribution 
> technique, and we have maintained the idea of Switch A for the crate 
> energy sum output path, and Switch B for the inbound 'common' 
> signals.(Clock(s), Trigger, Sync) for some time.  No work assignments 
> have been started for signal distribution hubs, but design research 
> effort has been started for the Switch B and Trigger Interface board 
> projects.  We continue to maintain the 'hub' hardware for various 
> F1TDC installations and for legacy users with (small) lab experiments 
> without the need for VXS, the 'hub' design is a simple solution.
>
> I will take this opportunity to mention that I will continue with 
> drawings for the readout 'system' with an emphasis on the Level 1 
> Trigger viewpoint.  There are plenty of design definitions to resolve 
> for the trigger system, and I think it would be an important working 
> group session for the October collaboration meeting.
>
> Please send your comments, suggestions, and flames at your earliest 
> convenience.
>
> Cheers,
> Chris
> cuevas@jlab.org
> ~~~~~~~~~~~~~~~~~~~~~~~
>
> Fernando J. Barbosa wrote:
>> Hello everyone,
>>
>>    I have attached a file that captures the pin allocations for the 
>> various VME modules. This document also elaborates on the signal 
>> distribution, either via a hub or a VXS switch card. I have also 
>> uploaded this document to the Hall D portal (Gluex-doc-857).
>>
>>    Although VXS caries additional upfront costs due to the connectors 
>> and backplane, the cost of a hub implementation may actually be 
>> higher if installation costs and reliability are considered. I, 
>> therefore, recommend that we proceed with the design of the VXS 
>> switch card signal distribution before spending valuable resources on 
>> signal distribution hubs. I believe that additional features can be 
>> explored on the design of the switch card given the I2C serial 
>> interface.
>>
>>    Please do not hesitate to send me your comments or corrections.
>>
>> Regards,
>> Fernando
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