Re: Hall D Electronics System Review - 14 March 2008, F326/327, 2:00p.m.

["C. Cuevas" <cuevas@jlab.org>]

Hi,

I agree, and my message was unclear.

You have the items listed below:
~~
1. Trigger System Diagrams
2. Signal Distribution (Global, VXS, Clock, Trigger, etc.)
3. Signal Distribution (SD) Module
4. Trigger Interface (TI) Module
5. Energy Sum (ES) Module
6. Energy Sum Processor (ESP)
7. SubSystem Processor (SSP)
8. Tagger Energy Processor (TEP)
9. Global Trigger Processor (GTP)
10. Track Subsystem Processor (TSP)
11. Global Trigger Crate
12. Software Support  & CODA
13. Test Strategies
~~
Items 2, 3, and 4 are part of the the trigger/clock/sync distribution 
section.
Items 5, 7, 9 and 11 are part of the Level 1 trigger system section.
Items 6, 8, and 10 are not modules, and the functions of energy sum, and 
track counting are incorporated into the SSP(Item 7)
Items 1, 12, and 13 need to be discussed so we should leave them on the 
agenda.

Thanks,
Chris
x5053
~~~~~~~~~~
Fernando J. Barbosa wrote:
> Hi Chris,
>
> It is great to see the progress towards the 'test-stand' 
> implementation. However, I would like to keep the agenda items as they 
> are. If a module does not yet exist, we will have to label it as such 
> and direct resources as necessary. All that I am suggesting is that we 
> keep in mind the final trigger implementation. I think you agree that 
> all the trigger-related modules that we know of or heard about are 
> listed.
>
> Regards,
> Fernando
>
>
>
>
> Chris Cuevas wrote:
>> Cheers!
>> I have a suggestion for the agenda list because several of the modules
>> listed do not exist.  I propose three sections outlined below and
>> hopefully we can consolidate these topics to reflect what will be
>> presented at the review.
>>
>> Trigger and Data Acquisition Systems
>> Level 1 (Creates the experiment trigger)
>>      FADC250
>>      (Crate) Energy Sum
>>      SubSystem Processor
>>      Global Trigger Processor
>>      Fiber Optic Distribution(Energy Sum)
>>
>>   Trigger/Clock/Synchronization Distribution
>>      Trigger Supervisor
>>      Clock/Trigger Fanout
>>      Fiber Optic Distribution(Clock/Trigger/Sync)
>>
>>   Data Acquition
>>      Data rates
>>      Event Building
>>      Network layout (Includes ROCs, Slow Control, and TermServers)
>>
>> The specifications and details of circuit board schematics, circuit 
>> board
>> layouts, parts lists/costs  etc can be included for each section listed
>> above.
>>
>> The present activities are focussed on designing the modules for the
>> 'test_stand'.  We have the two 20 slot VXS crates, and will produce at
>> least four more FADC-250 modules so that we can test a variety of
>> configurations with the new CODA libraries.  The prototype Trigger
>> Interface module will be used to provide test capabilities for the
>> proposed fiber optic distribution of the clock and trigger signals 
>> for the
>> two crate test stand.
>>
>> Thanks,
>> Chris
>> ~~~~~~~~~~~~~~~
>>
>>
>>
>>
>>
>> On Wed, 5 Mar 2008, Fernando J. Barbosa wrote:
>>
>>  
>>> Hello everyone,
>>>
>>> We will have our next meeting towards the upcoming Hall D system review
>>> in May next week This meeting takes place during the regular Hall D
>>> On-line meeting slot (F326/327 @ 2:00 p.m.). You may also recall that
>>> there is a requirement for 80% design completion for the CD-3 review
>>> this Summer.
>>>
>>> The goals of these meetings are to review the status, schedules and
>>> costs with the emphasis on, but not limited to, the technical aspects,
>>> requirements and specifications of the trigger system and signal
>>> distribution. These are the areas that require the most input at this
>>> time. We also need to consider supporting infrastructure with 
>>> regards to
>>> testing of the various modules by the end-users.
>>>
>>> The following is the agenda for this portion of the meeting (other
>>> On-line items will be discussed):
>>>
>>> 1. Trigger System Diagrams
>>> 2. Signal Distribution (Global, VXS, Clock, Trigger, etc.)
>>> 3. Signal Distribution (SD) Module
>>> 4. Trigger Interface (TI) Module
>>> 5. Energy Sum (ES) Module
>>> 6. Energy Sum Processor (ESP)
>>> 7. SubSystem Processor (SSP)
>>> 8. Tagger Energy Processor (TEP)
>>> 9. Global Trigger Processor (GTP)
>>> 10. Track Subsystem Processor (TSP)
>>> 11. Global Trigger Crate
>>> 12. Software Support  & CODA
>>> 13. Test Strategies
>>>
>>> Suggested Documentation for the updates are as follows:
>>>
>>> 1. Description of the system or module - describes the operation and/or
>>> shows where it is applied
>>> 2. Specifications - should be comprehensive but emphasize the main 
>>> tasks
>>> 3. Diagrams - system, block, wiring, etc.
>>> 4. Schematics
>>> 5. PCB
>>>
>>> I have created the appropriate directories in the M drive:
>>>
>>> 1. For most of this documentation, place your files in
>>> M:\halld\Electronics\Documents\TRIGGER or
>>> M:\halld\Electronics\Documents\SIGNAL_DISTRIBUTION (for clock, trigger,
>>> reset, distribution, etc. only).
>>>
>>> 2. For schematics and PCB CAD files, place your files in
>>> M:\halld\Electronics\PCBs\TRIGGER or M:\halld\Electronics\PCBs\SIGNAL
>>> _DISTRIBUTION.
>>>
>>> Regards,
>>> Fernando
>>>
>>>
>>>     
>>
>>