Re: Combined tracking meeting

[Gerard Visser <gvisser@indiana.edu>]

Hi Curtis,
	I read your doc, just wanted to mention that as far as the ADC125 is 
concerned there would certainly be an option either to have it be 14 
bits or to apply some nonlinear stage in the analog input signal 
conditioning. Actually 14 bits has for a long time been planned as the 
baseline pcb design so it can be stuffed either for 12 or 14 bits 
operation, so that all is trivial (except for the higher price of the 14 
bit chips). Nonlinear signal processing needs a lot of detailed 
discussion, it is not going to get into this summer's pcb layout, but I 
am pretty sure there will be enough room on the board to add something 
if we need to in a future version. Of course if the ADC voltage scale is 
made nonlinear the FPGA will also have to transform it back (with more 
bits) to linear form before integrating the charge, etc. But this should 
be feasible.
	Asking for only a factor of 20 in dynamic range sounds low, but I'll 
wait to hear details at the meeting...

	Gerard

Curtis A. Meyer wrote:
> Hi Everyone -
> 
>   there will be a combined tracking meeting on Monday July 28 at
> 1:30pm. I have created the Wiki page and put a couple of items
> on the agenda. Please add appropriate items as people see
> fit.
> 
>    - Curtis