Re: shaper gain

[Gerard Visser <gvisser@indiana.edu>]

Hi Fernando,
	Oh, one other point, and this is maybe worthwhile for others to 
consider too. The present "anode" setup of the shaper board, I believe, 
puts the full scale of the ADC at roughly 770 fC (instantaneous input 
charge, e.g. Fe55), as documented on page 2 of 
http://argus.phys.uregina.ca/gluex/DocDB/0007/000736/003/Receiver_Shaper_Setup_for_GPC01.pdf
	In other words, the "good linear range" of the ASIC is presently about 
39 to 52% of the ADC range, depending on what you call "good".
	With the proposed change, the "good linear range" of the ASIC should 
then be about 8 to 10 % of the ADC range. I'm not sure this is really 
what we want to do... (Although of course we can try it and see. I could 
be proved wrong!)

	Gerard

Gerard Visser wrote:
> Hi Fernando,
>         Ok, just to check, this will be setting the gain 1/5 of the present
> "anode" shaper gain, is that correct? (If not, please say...)
...