ADC125 P2 pinout

[Gerard Visser <gvisser@indiana.edu>]

Hi Chris, Fernando,
	I thought I'd sent this before but I checked, seems like I hadn't. My 
apologies. Here is the present plan for the P2 connector pins. Let me 
know if it needs discussion or modification. BUSY is intended as "almost 
busy" i.e. need not be acted on immediately, a couple more triggers are 
allowed. So, I suggest it be single-ended open-drain for a wire-or tie. 
If you want LVDS instead (or on additional pins) that's ok, just say it.
	CLK and TRGn +/- are differential CML inputs. In use, TRG0 can be like 
TRIG of ADC250, TRG1 can be like SYNC of ADC250, TRG2,TRG3 ignored. Or, 
up to four of them can be used for a fuller "trigger command input" as I 
have mentioned elsewhere. It's just a matter of FPGA programming. The 
TRG bits will be received by flip-flops clocked by CLK input. Pins A1/C1 
obviously have the best jitter performance by spacing to VME address & 
data lines.

	Gerard

ADC125__P2_pinout.pdf