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Struck ADC test clock source
Hi Fernando,
Per our discussion this morning Kim is going to make the test clock
board, right? I think this sounds great! It is the best way to move
forward without upsetting other schedules.
I have attached here my schematic sketch of what the board might look
like. Of course there are many ways to do it, maybe you already have
something else / something better in mind. I don't have any objections!
If you do care to follow the approach I sketch here, I will be more
than happy to review the schematic that Kim has entered prior to the
layout work. It's a pretty simple board but we should still avoid any
mistakes if possible.
The requirements of this board, I think, are the following:
1. Use an on-board LVPECL or LVDS differential-output oscillator module
of a very low jitter type (such as the Epson EG2102CA which is a SAW
oscillator). Frequency tolerance should be < 100ppm.
2. Fanout out to not less than three outputs using an LVPECL-LVPECL or
LVDS-LVPECL clock fanout part. I choose the 8314AGI-11 from IDT, it is
in stock at NuHorizons, it provides five outputs, this is surely enough.
Doing a fanout by a passive divider or something like that is also
possible, but an active fanout chip provides immunity against jitter on
one output due to reflections or noise input on the other outputs. Of
course we try not to inject noise or reflections into the other outputs
so this is maybe overkill, but it is anyway cheap.
3. For each output, convert it from from ECL to a single-ended NIM
output, or to differential NIM outputs if you prefer (in which case we
just stick a terminator in one half). [Note this is why I run the "PECL"
oscillator and fanout chip from -6+3.3 to -6 V.]
4. Power from something reasonable like a 6V wall adapter.
I think my design will meet these requirements.
I don't know if the oscillators will be ordered by you or Curtis.
Whoever order's them, please get 5 extra for my use on the ADC board and
prototyping.
Thanks,
Gerard
StruckTestClock.pdf