Hall D Electronics System Review - meeting summary

["Fernando J. Barbosa" <barbosa@jlab.org>]

Hello everyone,

This is a summary of our recent meeting towards the upcoming Hall D 
system review in May. You may recall that there is a requirement for 80% 
design completion for the CD-3 review this Summer.

The goals of these meetings are to review the status, schedules and 
costs with the emphasis on, but not limited to, the technical aspects, 
requirements and specifications of the trigger system and signal 
distribution. These are the areas that require the most input at this 
time. We also need to consider supporting infrastructure with regards to 
testing of the various modules by the end-users.

I should stress the fact that, although the trigger system is relatively 
small in total hardware, the effort required and the number of resources 
is not - it will be a very important part of the review.

The agenda, date and charge for the review are not yet known. It is 
likely, however, that the review will follow a format similar to 
previous ones with emphasis on the overall implementation, review the 
most critical links, safety, cost, support and schedules.

We agreed to have regular meetings every two weeks which should allow us 
to meet  4 times prior to the review.

Meeting Summary:

1. Trigger System Diagrams - Not presented. Chris will have these 
diagrams, representing the physical layer, ready in two weeks and 
present at our next meeting. Dave D. will need to provide a description 
of the upper layer (?) describing where the user may form the triggers 
in L1 and above. There is also a question of the TOF crates - How to 
implement the trigger and the track count part.

2. Trigger Timing - The trigger latency is around 2 us (from a previous 
estimate of 2.5 us). The consensus is to keep the 2.5 us spec. The F1TDC 
(3.7 us) and the flash (8 us) meet the spec.

3. Signal Distribution (Global, VXS, Clock, Trigger, etc.) - 
documentation in progress.

4. Trigger Interface (TI) Module - documentation in progress. Ed should 
have a prototype module in 1 month and tested in time for the review.

5. Energy Sum (ES) Module - no report.

6. Signal Distribution (SD) Module - no report

7. ROC - David A. reported that he is working with new ROCs. These 
should meet the 2eSST 320 MBPS transfer rate but we need to verify if a 
system with F1s and fADC250s can meet the spec. The F1s and fADC250s 
have been designed to meet the spec. The most data intensive transfers 
will occur on crates with the fADC125 because of the channel count per 
module (72) and the high occupancies.

8. Energy Sum Processor (ESP) - no specific report. Dave D. will have 
meetings with Chris, Ben and Ed, to move the implementation forward.

9. SubSystem Processor (SSP) - no report . See 8.

10. Global Trigger Processor (GTP) - no report . See 8.

11. Global Trigger Crate - no report . See 8.

12. Track Subsystem Processor (TSP) - no report . See 8.

13. Tagger Energy Processor (TEP) - no report . See 8.

14. Software Support  & CODA - David A. will provide the CODA drivers 2 
weeks after receiving a module. Ed and Hi are finalizing the tests and 
debugs and will provide one of  the fADC250 modules to David A. in a 
week. Expect a CODA readout by 21 March 2008.

15. Tests. - see 14.

In my opinion, we have very little documentation in a form that can be 
presented and defended in a formal review. We really need to work on 
this over the next 4 meetings. As I am tasked with collecting this 
information, let me suggest the following documentation, and as appropriate:

1. Description of the system or module - describes the operation and/or 
shows where it is applied
2. Specifications - should be comprehensive but emphasize the main tasks
3. Diagrams - system, block, wiring, etc.
4. Schematics
5. PCB

I have created the appropriate directories in the M drive:

1. For most of this documentation, place your files in 
M:\halld\Electronics\Documents\TRIGGER or 
M:\halld\Electronics\Documents\SIGNAL_DISTRIBUTION (for clock, trigger, 
reset, distribution, etc. only).

2. For schematics and PCB CAD files, place your files in 
M:\halld\Electronics\PCBs\TRIGGER or M:\halld\Electronics\PCBs\SIGNAL 
_DISTRIBUTION.

Please feel free to create subdirectories inside the above links for 
separate modules, i.e. GTP, SSP, etc. You can always send me the 
information and I will gladly place it in the appropriate area.

Thanks,
Fernando


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