Re: P0 connector, busy questions

[Chris Cuevas <cuevas@jlab.org>]

Hall D Electronics:

Gerard,

The FADC-250 parts list shows #1410147-1 as a Tyco part number for P0.

As for the 'busy' signal to the B switch board please use DP29+/- (A15;
B15).  These are presently defined as LVDS_Status_Out and at our last
FADC/Trigger meeting on Friday we have come to 'final' agreement on the
signal definitions for the Trigger Interface slot (PP18) and of course the
signal definitions for bot the Energy Sum Module(Switch-A) and
Clock_Trigger Distribution Module(Switch-B). I think your plan to
implement the capability to receive/send the clock/trig/busy signals to P2
is a good idea.


The documentation for the
overall trigger, clock, and network system layout is progressing and the
drafts will be ready soon.  The VITA 41 documents certainly defined the
pair assignments, but for our crate system we need a two page table that
shows the signal names from each PayloadPort to each switch slot.  Designs
for the Trigger Interface module, full crate energy sum module and
ClockTrigger distribution module are a work in progress, so we will
finalize the signal assignments very soon.

Regards,
Chris
~~~~~~~~~~~~~~~~~~~~~~~


On Tue, 4 Mar 2008, Gerard Visser wrote:

> Hall D Electronics:
>
> Hi Fernando,
> 	Please confirm, the P0 connector is supposed to be AMP # 1410147-2,
> right? I don't have a copy of the VXS specifications document yet, I
> deduced this from AMP's webpage and some other docs I found on the web.
> 	Also, I am thinking that I should send the ADC125 busy output on either
> G13(SE7) or G15(SE8) as an open-drain output. Can you confirm, these
> lines go on the backplane to the correct switch slot, the same one as
> the TRG,CLK lines you have chosen for FADC250? I suppose if the FAD250
> implements a busy out it will be LVDS on the LVDS_STATUS1_OUT_P0 line
> and it's complement, right?
> 	I'm trying to finish off the P0 connections on the ADC125 schematic,
> I'll look forward to hearing from you on this. Thanks,
>
> 	Gerard
>
> p.s. Executive summary for the rest of you, ADC125 will take clock and
> trigger from, and send busy to, either P2 or P0/VXS,
> software-selectable. This also means I won't require a VXS crate for
> testing, except of course just to test the P0/VXS connections will
> require a VXS crate and suitable trigger/clock "switch" card. The
> trigger/clock "switch" card design will presumably be one design that
> can work with ADC125 or FADC250.
>