VME/VXS P0 pinout JLab Standard

["Fernando J. Barbosa" <barbosa@jlab.org>]

Hello everyone,

I have updated the P0 pinout information on doc 857 of the Hall D 
portal. This is the standard we have discussed on the conference call 
and in subsequent meetings. This information is easily accessible 
through the wiki 
(http://www.jlab.org/Hall-D/software/wiki/index.php/Electronics#Electronics_Subsystems), 
last item under Crates & Racks.

The changes were:
1. changed TRIG to TRIG1 and from LVDS to LVPECL on DP23+/-
2. changed SYNC from LVDS to LVPECL on DP24+/-
3. changed SPARE to TRIG2 and from LVDS to LVPECL on DP26+/-

Please note that LVPECL receivers must not be damaged if un-powered with 
drivers powered and receivers must not oscillate if the driver PCBs are 
not installed in the crate. I added this note to the document.

This document constitutes the standard for the VXS P0 usage at JLab. Let 
me know if you have any questions.

Regards,
Fernando
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