VXS SD Module

[Gerard Visser <gvisser@indiana.edu>]

Hall D Electronics:

Hi Chris,
	It's good to see the description/requirements document for the SD 
module posted. I have been looking forward to this. I have some comments 
if that's ok...
	1. Page 3, introduction. The SD module has _nothing_ to do with the 
trigger output data path from the FADC250 (well, apart from the fact 
that it needs _some_ clock to do that, of course). I think all that 
discussion should be removed from this document. On the other hand, the 
SD does feed trigger/clock to ADC250, ADC125, and F1TDC, probably the 
latter two should at least be mentioned here.
	2. Page 3, section 3.0. I'm not clear what is implied by "trigger and 
sync ... can be dynamically changed before registering".
	3. Busy out from SD to TI: In the text P.3 this is LVDS, in fig 2 this 
is LVPECL, so one of these is wrong...
	4. Negative ECL is shown for front panel trigger out, yet there is no 
negative supply voltage listed in table 1, probably this is an omission?
	5. For SD to FEE boards, trigger bits are stated to be LVDS on p.3 and 
in fig 5 and fig 3c, and are stated to be LVPECL in fig 4 ("spec sheet", 
figure caption omitted) and in p.10 section 4.0.6. As I have previously 
argued in our meeting some weeks ago, I would still strongly argue to 
use LVPECL in reality. But whatever your choice, the document is quite 
confused on this point.
	6. Can we just change the name of "STATUS_OUT" from FEE boards to 
"BUSY". This is what we are using it for, right? I think it is 
unnecessarily confuing to give the busy lines a name like "status out".
	7. Section 4.0.1, I would assume that the clock selection is to be done 
over I2C just like any other setup parameter... "JTAG" here is probably 
a typo?
	8. p3, bottom - "JTAG port to program the FPGA". Have you considered to 
do that over I2C? It would be easier if you can make a design change and 
implement to all boards without physical access... Of course you could 
have some kind of permanent JTAG connection in mind for the system, but 
that seems to me more complicated than implementing an I2C controlled 
design download. Especially the more so if you already plan to have a 
microcontroller on the board to handle the I2C...
	9. What is become of all the "skewing" stuff that was discussed, 
intended to remove slot-slot skew? I am absolutely quite happy without 
it, do not get me wrong. But on the other hand if you do still intend to 
have such a function, it really must be included in the block diagrams 
fig 3a/b and in the description 4.0.6, and I still would 
expect/"require" that it be done in a way which does not introduce skew 
between the clock and the three trigger bits within one FEE (payload) 
slot. I still expect the three trigger bits to be registered by the 
clock line as the last thing done in the SD to send to each slot. Do I 
need my mind changed on this? (I think not, you agree in fig "4".)
	10. Regarding the CBLT token (4.0.5), what causes the token to be set? 
Is this going to have to be done over I2C? Or is there a hard line for 
TI to SD to do it? In the latter case, it seems to be missing from the 
various block diagrams fig 2, 3x... In the former case, is it fast enough?
	11. What is TRIGLINKTX and what is Trigger2??
	12. Busy mask probably needs to be mentioned under 5.0, just as you 
have mentioned the CBLT mask.

	Hopefully this is a complete list of questions, I look forward to 
hearing from you or checking out the revised document. Thanks!

	Gerard