F1TDC update (fwd)

[Elton Smith <elton@jlab.org>]

---------- Forwarded message ----------
Date: Tue, 19 Jun 2001 11:40:08 -0400
From: Fernando J. Barbosa <barbosa@jlab.org>
To: Chris Cuevas <cuevas@jlab.org>, Ed Jastrzembski <jastrzem@jlab.org>,
     Elton Smith <elton@jlab.org>
Subject: F1TDC update

    Hi, all. I have made considerable progress on the front end of the
F1TDC and considerable testing lies ahead. My first priority is to develop
a 1:1 prototype of the front (connectors to F1s) and ancillary circuitry
(Power up reset monitor, clock distribution, Synch distribution, etc)
before merging the design with Ed's section. No F1s will be installed,
though. The reason for such prototype is primary due to timing
characteristics, get the correct signal delays and terminations. Because
of the fast signal characteristics (260 pS gate delays, 130 pS rise and
fall times and less than 1 pS jitter per gate) required for good timing
and low overall jitter, transmission line architecture is required and
will be implemented.

    I will be away on vacation until July 2nd. Best regards to all,


        Fernando
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