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F1TDC Tests (fwd)





---------- Forwarded message ----------
Date: Mon, 17 Jun 2002 15:28:05 -0400
From: Fernando J. Barbosa <barbosa@jlab.org>
To: Ed Jastrzembski <jastrzem@jlab.org>
Cc: James Proffitt <proffitt@jlab.org>, Bill <gunning@jlab.org>,
     Chris Cuevas <cuevas@jlab.org>, Dia Williams <dwilliam@jlab.org>,
     Elton Smith <elton@jlab.org>, Jeff Wilson <wilson@jlab.org>
Subject: F1TDC Tests

    Hi, Ed. The following are generalized test/assembly steps for the F1TDC, as we discussed last week. I have also assigned people who I believe will be involved in these various steps. Please, review and feel free to modify accordingly.

Board 1
1.    Assemble (Jlab) front-end components relevant to preliminary tests - Jeff, Bill - Pass
2.    Front-end preliminary tests - Jeff, Fernando - Pass

Board 2
3.    Assemble (Industry) BGA - Jeff, Ed - Underway
4.    Assemble (Jlab) back-end components and one FIFO for later readout of one F1 chip (channels 1-8) - Jeff, Bill
5.    Test VME interface and other back-end functions - Ed, James

6.    Assemble (Jlab) front-end components relevant to read-out of one F1 chip (channels 1-8) - Jeff, Bill
7.    Signal integrity tests for channels 1-8 - Fernando
8.    8-channel (120 pS LSB) and 4-channel (60 pS LSB) resolution tests - Ed, Dave

Boards 3 and 4
9.    Assemble (Industry) two complete boards - Jeff, Bill, Dia, Ed, Fernando
10.    Complete tests - Fernando, Ed, Dave,.........


    I have provided Jeff and Bill with a list of the components needed for step 6 as I will be on vacation from June 20th through July 8th.

    Best regards,
        Fernando
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