[Fwd: Re: Fast ADC's for Gluex]

[Elliott Wolin <wolin@jlab.org>]

-------- Original Message --------
Subject: Re: Fast ADC's for Gluex
Date: Fri, 13 Feb 2004 14:04:31 -0500
From: Paul Smith <ptsmith@indiana.edu>
To: wolin@jlab.org
References: <200402131815.i1DIExw10062@xanadu.physics.indiana.edu>

Hi,

I know about these, plus there is a recent 14 bits at 125 MSPS from
Texas Instruments, and an 8 bits at 500 MSPS from Atmel.

All of these cost more, use more power, and are in a larger package
than the SPT7721 on the prototype.

One consideration is the dual port memory in the FPGA; if the data
width isn't a power of 2 you can't use all the memory bits in the part,
so you have to go to a larger part to get enough words.  For example,
if you used a 10 bit FADC, you would have to go to a 16 bit wide dual
port memory in the FPGA, and "waste" 6 bits of data width.

The SPT7721 also isn't a "classical" (256 comparators) flash
architecture either, this doesn't really matter.

I'm not adverse to a different FADC chip than the SPT7721, but I think
it's the best deal in price/performance at this time.  My next favorite
would be the 8 bit, 500 MSPS from Atmel, but they cost about 4 times as
much.

The problem with 210 MSPS is that it isn't a sub multiple of the
accelerator clock - I believe we would be better off syncing to the
accelerator.

This is an issue for the F1 TDC as well.  I asked Ed once if the F1
could be synced the accelerator clock so the least count would be 62.5
pS (instead of 60).  My recollection was that he was going to look into
it.  Could you ask about this?