Re: Frontend & Thermal Management HallD (fwd from Mitch Newcomer)

[Elton Smith <elton@jlab.org>]

---------- Forwarded message ----------
Date: Fri, 02 Feb 2007 17:57:31 -0500
From: Mitch Newcomer <mitch@hep.upenn.edu>
To: John Schaapman <jsch@phys.ualberta.ca>
Cc: Fernando J. Barbosa <barbosa@jlab.org>,
     Elke-Caroline Aschenauer <elke@jlab.org>,
     Daniel S. Carman <carman@jlab.org>, Simon Taylor <staylor@jlab.org>,
     Gerard Visser <gvisser@indiana.edu>, Elton Smith <elton@jlab.org>,
     Curtis Meyer <cmeyer@ernest.phys.cmu.edu>,
     HallD _Tracking_HW <halld-tracking-hw@jlab.org>
Subject: Re: Frontend & Thermal Management HallD

John  (and  all)   very  fair question:
  we have had several difficulties with the Cadence design kit supplied
by MOSIS.  Evidentally most users
are doing scalable digital design, not analog.    We have fixed the
problems we can and made work arounds for others.
ex. a) The poly resistor calculator doesn't work and indicates improper
values on the schematic, but when spice actually
runs, the value is correct.  Design rules doesn't allow a 5um wide
(poly) resistor larger than 1.4K so we need to string  many
together  to get  large values.
  b) We were somehow limited to the number of transistors that could be
arrayed without giving a DRC,  33 transistors in an
array would work,  but the next one wouldn't.    These kind of problems
were new to the students and it took a while for
them to perculate up to Nandor and I slowing the normal rate of progress
down.
   We do have a layout extracted single channel netlist with parasitcs,
but are stuck with making our own PAD library. Usually
a vendor provides a pad library with  single, corner and protected pads.
These are not included in our Cadence tool kit.   There
is a pad library  document  from a company called  Tanner  but it isn't
in a  Cadence useable format.
We are making our own library.   We need to be careful not to violate
our NDA's so it's not straight forward to just transfer
files from other  groups into our files.  We found pad library files
publicly available in  .gds format and pull them into
cadence but they did not pass our DRC's.  So we are returning to work we
did  using  TSMC in 2002, using those pads after
checking to see that they don't violate the current design rules and
moving forward.
   One of the students working on the project graduated  and has left.
The other  was stranded in India for several days beyond
his planned return date of Jan 20, which led me to believe he wasn't
coming back.  Last week Nandor Dressnandt and I took
over the design and have been putting in significant effort on it every
day.    MOSIS requires the design be submitted two weeks in
advance.  We are close, but not close enough.    MOSIS will perform the
final  DRC checks, so this should double ckeck our
if  "fixes".
When it became obvious to me that we wouldn't be able to send MOSIS a
fialized set of files by Jan 31 I decided to add a
change to the current bias generators to reduce the succeptibility of
the design to the supply voltage.  This will require a small
amount of additional space and doesn't affect the parts already in the
layout so we will put this in the single channel design before
arraying the 8 channels together.
  -  Mitch


John Schaapman wrote:
> Hi Fernando,
>   I have just a few comments on your excellent report.
>
> section:
>
> 2. The ASIC preamp.
>    Has Mitch Newcomer indicated that the previously mentioned submission
> date to MOSIS of Feb 12 will be missed and why?
>
> 3. The Preamp Card
>    a) I'd just like to clarify that two versions of the 24 channel card
> will still be required due to the fact that the input signal polarities
> of the anodes and cathodes are opposite. A third version may be needed for
> the CDC if it is in the chamber gas and requires low outgassing material.
>    b) The input connector could be a source of problems since there are
> not enough signal grounds. Adjacent signal pins could create unacceptable
> crosstalk and too few grounds could lead to signal reflections and more
> crosstalk. I realise that there is very little space but this arrangement
> should make us nervous.
>
> 4. Thermal Management.
>
>    You have specified a power supply input of 3 volts minimum for operation and
> your thermal calculations so far. It would be nice to know at some point what
> the maximum supply voltage would be due to thermal limitations. This would help
> set the tolerances required for the power supplies and distribution system.
>
> John
>
>
>
>