fADC-100 questions

["Fernando J. Barbosa" <barbosa@jlab.org>]

Hi Gerard,

In preparation for the chamber review next week, could you provide a 
block diagram of the board? Or maybe a brief description of how you plan 
to package the electronics?

The board is very dense at 72-ch or 36 chips and 3 connectors (50 pin). 
How many channels/connectors go on the mezzanine board? How many 
FPGAs/FIFOs go on the mezzanine? How many data/control lines do you need 
and how to connect the main and the mezzanine boards?

Thanks,
Fernando
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