Flash ADC Timing

[Matthew Shepherd <mashephe@indiana.edu>]

Hi all,

The study I was referring to has been linked to the FCAL page here:

http://www.jlab.org/Hall-D/software/wiki/index.php/FCAL

This work was done about 3 years ago and claims a resolution of about  
~160 ps can be achieved.  This is far better than is actually needed  
to push down backgrounds.  I think Scott had in mind another  
application:  using the FCAL to determine the event start time.  The  
algorithm does a transformation of the leading edge of the pulse to  
determine the start time and depends on having the two samples before  
the peak on the leading edge.

I believe Paul had planned to implement this in a simple lookup table  
which would require about 65K of memory on the chip.  Perhaps that  
could be optimized even more.  It was never investigated in detail  
mainly because it seemed like something relatively easy to  
implement.  All of these buffers will need some processing -- the  
drift chambers will also depend on the timing algorithms that are  
built into the flash ADCs.

-Matt