Re: Die Pad Layout

["Fernando J. Barbosa" <barbosa@jlab.org>]

Hi Mitch,

    I have a preliminary board layout based on the ASIC information that 
we developed over the past few months. I am attaching the pinout for the 
GAS-1 ASIC. Note that the NC pins are not committed as of yet. Please 
feel free to assign the pins as you determine the best fit for the die 
and send me your final pinout. Once I have this, I will finalize the 
layout of the preamp card.

    In view of the final design, we would also like to have a 
differential calibration input to all channels. This could be very 
similar in function to the one you implemented on the ASDQ: a short 
differential (LVDS?) input pulses a constant current into all channels 
or odd/even channels where a bias voltage sets the magnitude of the 
current. What level of accuracy can you obtain considering the 
manufacturing tolerances?

Best regards,
Fernando

Mitch Newcomer wrote:
> Fernando and Lars,
>                                 we are now at the chip level and are 
> considering the die pad layout.   Is there
> a board design in progress?  Has the packaged chip pinout been 
> committed at this point.   We would like
> to just lay down the die pads where they appear on the sides of the 
> die.   This  may affect the package pinout
> on the sides of the chip, not a lot, just switching pins etc.   We 
> forsee  4  current setting pins and one
> shaping pin. This will allow the user to trade off  shaping and  power 
> on the fabricated device.  It
> seems to work nicely. 
> I will have a short power point to show our basic layout and several  
> performance plots hopefully by Friday.
> Next week I'll be at CERN, but available by email.  
>                                                                                                             
> Mitch

gas-1.pdf

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