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Re: Fw: Electronics Workshop Mar 28 Agenda and Topics List
Hall D Electronics:
On Thu, 22 Mar 2007, Lars Holm wrote:
Dear Lars et all,
I have booked room L102-104 from 9.00 - 20.00 for wednesday, this room has
also video capabilities, so if somebody wants to join from the outside no
problem. As I pointed out already I also think the time from 1.00 to
18.00 is not long
enough to cover all the topics, I even think 2030 minutes per topic is not
long enough. I personnaly would like to discuss in detail the schedules
and manpower needed and working on different items, because we run into
problems with our schedule, which is not yet a problem but will be one
next year as all the variance reports will go to DOE.
Cheers and looking forward to see you all next week
elke
p.s. can you send me please ones more the really final agenda, because I
got confused which on is the real one.
> Electronics Meeting - March 28, 2007
>
> preliminary list of topics - version 5 Mar 22
>
> Summary Chart and initial discussion Fernando/Lars
> - what topics are missing from list?
>
>
> 1. Drift Chamber Preamp ASIC John
> - UPENN ASIC development summary ppt from Mitch
> - when are chips available? 12 weeks after submission
>
> - ASIC testing/allocation plans
>
> Discussion - including ASIC next version
> - x 5 gain - pin select for FDC cathode readout - 2 weeks design time
> - discriminator - pin select for FDC anode readout
> - 1-2 months design time
> - do we want oneshot or time over threshold output?
> - timeline for development and production? after GAS-1 tested/modified
> likely next earliest submission date Nov 5, 07
>
> 2. FDC daughterboard - space and thermal constraints etc. Fernando
>
> 3. Drift Chamber 100 MSps fADC Gerard
> - update
> - what info is needed to continue the design?
>
> 4. Constant Fraction Discriminators Lars
> - commercial units - where would they be good enough ?
> - custom fast CFD - where are they needed?
>
> 5. Jlab fast electronics Chris
> - F1TDCs mods for Hall D requirements
> - update on fADC250s
> - Energy summing/track counts
> - Summing module (VXS)
> - Global clock/timing and trigger systems
>
> 6. Trigger system architecture Dave Doughty
>
> 7. Clock/Trigger Distribution Ed J.
> - local (crate level) distribution and trigger info to readout controller
>
> Discussion Clock
> - what frequencies are required? 40, 100, 250 MHz?
> - what jitter levels are acceptable for the various applications
> - what are the skew requirements between modules and systems?
> - how will this skew be measured and corrected for?(calibration system?)
>
> 8. Calibration System discussion
> - what is it supposed to accomplish?
> - how can this be done?
> - How is it controlled/distributed?
> - how much skew is allowed for the various systems
> and how is it corrected for?
>
> 9. Scalers discussion
>
> - could it be done inside the fADC250s?
> - SIS3800 32 ch 32 bit 200 MHz scaler VME module
>
> 10. SiPM George Lolos??
> a.) BCAL - cooling, power, risetimes
> - do we need 60 ps TDCs?
>
> 11. Cabling issues discussion ??
> - FDC cable type - connectors
> - layout priorities - which need to be shortest due to signal quality,
> timing or cost?
>
> 12. Signal splitters John
> - need 3,648 channels (i.e. 10,944 connectors and 7,296 Lemo cables!)
> - do we want passive or active splitter?
> - connectors in/out? BNC in, Lemo out? front/back?
> - form factor- modular or seperate boxes?
>
> Close Out
> - decide priorities
> - alocate orphans
> - manpower needs
>
> Lars Holm Office: 780-492-5426
> Department of Physics, FAX: 780-492-3408
> University of Alberta email: lars@phys.ualberta.ca
> Edmonton, Alberta, CANADA T6G-2N5
>
> Lars Holm Office: 780-492-5426
> Department of Physics, FAX: 780-492-3408
> University of Alberta email: lars@phys.ualberta.ca
> Edmonton, Alberta, CANADA T6G-2N5
>
>
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