Re: Flash ADC Status - Front-end Test Results (fwd from Dave Mack)

[Elton Smith <elton@jlab.org>]

Hall D Electronics:



---------- Forwarded message ----------
Date: Mon, 9 Jul 2007 11:43:55 -0400 (EDT)
From: Dave Mack <mack@jlab.org>
To: Fernando J. Barbosa <barbosa@jlab.org>
Cc: Bodo Reitz <reitz@jlab.org>, David Doughty <doughty@jlab.org>,
     Elke-Caroline Aschenauer <elke@jlab.org>, Elliott Wolin <wolin@jlab.org>,
     Elton Smith <elton@jlab.org>, Latifa Elouadrhiri <latifa@jlab.org>,
     Robert Michaels <rom@jlab.org>, Serguei Boiarinov <boiarino@jlab.org>,
     Stephen A. Wood <saw@jlab.org>, Volker Burkert <burkert@jlab.org>,
     Xiaochao Zheng <xiaochao@jlab.org>, Chris Cuevas <cuevas@jlab.org>,
     David Abbott <abbottd@jlab.org>, Ed Jastrzembski <jastrzembski@jlab.org>,
     Hai Dong <hdong@jlab.org>, HallD _Tracking_HW <halld-tracking-hw@jlab.org>,
     halld-electronics@jlab.org
Subject: Re: Flash ADC Status - Front-end Test Results

	Fernando,

	The noise results are very impressive. Do you have any idea how
this will map to a 12-bit ADC?

	The linearity and cross-talk look promising but need to be
quantified. Let us know when we can help.

	congratulations,

	Dave



On Tue, 3 Jul 2007, Fernando J. Barbosa wrote:

> Hello everyone,
>
>     I have attached a test report on the characterization of the
> front-end section of the flash ADC. The fADC-250 prototype front-end
> meets or exceeds the design specifications.
>
>     There is still a lot of work ahead before we can release the ADC for
> user tests. Tests of the data processing section,  the energy sum,
> trigger, VXS and full VME readout and register settings are continuing.
>
>     Do not hesitate to contact me if you have any comments or suggestions.
>
> Regards,
> Fernando
>
>