Re: PCB form factor (fwd)

[Elton Smith <elton@jlab.org>]

---------- Forwarded message ----------
Date: Tue, 27 Feb 2001 16:42:44 -0500
From: Fernando J. Barbosa <barbosa@jlab.org>
To: Paul Smith <paul@xanadu.physics.indiana.edu>
Cc: Ed Jastrzembski <jastrzem@jlab.org>, Elton Smith <elton@jlab.org>
Subject: Re: PCB form factor

Hi, Paul,

    I am planning to attend the collaboration meeting and I hope the group
can reach a consensus resolution on what form factor, standards, etc. we
plan to use.
    Regarding the TDC resolution, you are absolutely right as for the
typical resolution of 120 pS and 60 pS. Better resolutions can however be
attained by choosing chips and performing some fine tuning of the substrate
voltage on the F1 chip. So, it is my fault to refer to the F1 specs as for
the best performance.
    As for paralleling these chips, I don't think we can do it easily. The 8
low resolution channels are internally combined to provide 4 high resolution
channels. Each channel can be programmed individually for delay in 64 steps
for up to 1 LSB. This is the easy part. The hard part would require precise
buffering of the combined inputs, reading the contents of the hit FIFOs,
processing, interpolation and combining to provide the required resolution.
    Best regards,
        Fernando

----- Original Message -----
From: "Paul Smith" <paul@xanadu.physics.indiana.edu>
To: <ptsmith@indiana.edu>; <barbosa@jlab.org>
Cc: <jastrzem@jlab.org>; <elton@jlab.org>; <doughty@pcs.cnu.edu>;
<task-d@dustbunny.physics.indiana.edu>
Sent: Tuesday, February 27, 2001 2:18 PM
Subject: Re: PCB form factor


> Hi Fernando,
>
> Are you planning to attend the Hall D collaboration meeting next month?
I'll be
> giving a brief presentation on the ADC R&D.  I've asked for you to be
placed on
> the agenda to give a brief presentation on the TDC project.  Also, there
is an
> electronics working group session scheduled which I hope you, Ed and
hopefully
> other JLab DAQ people can attend.
>
> There are also the weekly Hall D teleconferences.  It would be great if
you or
> someone from the JLab electronics/DAQ group could participate in these.
>
> One of the things I'd like to discuss at the working group session is the
"form
> factor" and bus standard.  If the ADCs are indeed some flavor of VME,
9Ux400mm
> probably makes the most sense.  However, I would like to at least discuss
> whether VME makes sense for the Hall D front end electronics.  A lot of
> commercial development is going in the Compact PCI format.  I question
whether
> we even need a parallel bus/crate structure at all.  There are several
high
> speed serial network standards now with faster data rates than VME or PCI.
>
> I thought the F1 chip resolution was 120/60 pS?  Are they really 100/50 pS
now?
>
> 60 pS is believed to be marginal for the Hall D TOF system.  I wonder if
there
> is any way to use 4 F1 channels in parallel to achieve 30 (25?) pS?
>
> See you in March.
>
> Paul
>
>
> >
> >Hi, Paul. How are you? I hope things are moving well on your project(s).
> >    We are presently finalizing the specifications on the TDCs and it
would be
> nice if the ADCs and TDCs could share the same DAQ system. At present, the
TDCs
> may be used in low resolution mode (64 channels, 100 pS resolution) or
high
> resolution mode (32 channels, 50 pS resolution) and these cover all
requirements
> for Hall D, as well as, future upgrades to the existing Halls. VME64X has
been
> chosen as the interface standard, although some questions still remain.
One of
> these concerns the form factor. A 6U form factor seems to fit our TDC
> requirements. Have you chosen a form factor for the ADCs? I believe the
ADCs
> will require more board space, maybe a 9Ux400 mm. Is this reasonable? For
> standardization, we may have to implement the TDCs in this same format so
that
> TDCs and ADCs can be used on the same crate, if needed. Standardization of
> crates may also lower the cost slightly due to the economy of scale.
> >    Best regards,
> >
> >        Fernando
>
>