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Re: Combined tracking meeting
Hi Gerard and Mitch,
I think it would definitely be helpful to have some Garfield studies
performed on the CDC for the various operating conditions. I am also of
the opinion that we should definitely plan for some beam studies with
the GAS-2. I know it takes resources but there is a lot involved here.
As you know, there is a test beam at BNL that we can plan for - I have
used it while at BNL a number of years ago while developing the
"predecessor" to the CDC and it provided invaluable data. The next small
CDC prototype could be slated for this tests.
I think it is also a good suggestion to ask Mitch about his experience
with various developments and if a 14-bit ADC is reasonable or overkill.
Mitch could you comment on this?
Certainly the 14-bit option is better than any additional circuitry for
a non-linear transfer function. The total cost increase would be about
$50k! That's a lot of money, for sure, and this points to the fact that
we really need additional studies, as I suggest in the first paragraph.
I think you also share that sentiment.
Regards,
Fernando
Gerard Visser wrote:
> Hi Elke,
> From the quote which I obtained last year, it is about $15 more
> per channel to have 14-bit ADC's on the board. There is (according to
> spec documents) no change to the power dissipation. [It is apparently
> the same chips, just tested to different level of performance that you
> buy.] It is probable the price will go down, probably not by quite
> that much though.
> Nonlinear response will cost much less than $15 per channel, as
> long as it fits on the same basic board architecture (which depends on
> the details of what we would want to do, of course).
> I agree also, the ASIC does some nonlinear transformation, but on
> the other hand _that_ may not be very precisely controlled (for
> temperature, matching, whatever...). Also, ideally the nonlinearity
> would be introduced after all shaping filters so that it can be
> precisely and easily un-done by a lookup table in the FPGA, to allow
> for integrating the pulse. If the nonlinearity is introduced earlier,
> then un-doing it requires some sort of nonlinear digital filter not
> just a lookup table.
> One final comment, probably it would raise eyebrows to say that we
> really need 14-bit resolution from a drift chamber ADC...? We should
> for instance get some opinions from Mitch on that. Of course I will be
> happy if we do use 14-bits.
>
> - Gerard
>
> Elke-Caroline Aschenauer wrote:
>> On Wed, 23 Jul 2008, Curtis A. Meyer wrote:
>>
>> Dear Gerard,
>>
>> how much more money are we talking for 14bit vs 12bit. Also keep in mind
>> we will not buy the boards before FY11, so mybe the prise than for 14bit
>> will be the same as now 12bit, but that is speculation on my side.
>> I also prefer even if there is a bit of more money involved to do the
>> easy
>> straight forward solution instead of a more complicated one. Curtis
>> don't
>> you want for dE/dx all the signal very well measured.
>>
>> cheers elke
>>
>>
>>> Date: Wed, 23 Jul 2008 16:49:09 -0400
>>> From: Curtis A. Meyer <cmeyer@ernest.phys.cmu.edu>
>>> To: Gerard Visser <gvisser@indiana.edu>
>>> Cc: GlueX Tracking <tracking@gluex.org>
>>> Subject: Re: Combined tracking meeting
>>>
>>> Hi Gerard -
>>>
>>> thanks for your comments. Actually, the factor is 60, but if we are
>>> willing to compromise on the slow, forward going protons, we could
>>> squeeze it.
>>>
>>> I also talked to Fernando about the non-linear aspect, and he also
>>> mentioned that the ASIC will do that for us at some level. It would
>>> be good to understand all of the effects involved. Given the option of
>>> stuffing the ~45 CDC modules with 14-bit chips might be a good
>>> option to consider.
>>>
>>> Cheers - Curtis
>>> On Wed July 23 2008, Gerard Visser wrote:
>>>> Hi Curtis,
>>>> I read your doc, just wanted to mention that as far as the
>>>> ADC125 is
>>>> concerned there would certainly be an option either to have it be 14
>>>> bits or to apply some nonlinear stage in the analog input signal
>>>> conditioning. Actually 14 bits has for a long time been planned as the
>>>> baseline pcb design so it can be stuffed either for 12 or 14 bits
>>>> operation, so that all is trivial (except for the higher price of
>>>> the 14
>>>> bit chips). Nonlinear signal processing needs a lot of detailed
>>>> discussion, it is not going to get into this summer's pcb layout,
>>>> but I
>>>> am pretty sure there will be enough room on the board to add something
>>>> if we need to in a future version. Of course if the ADC voltage
>>>> scale is
>>>> made nonlinear the FPGA will also have to transform it back (with more
>>>> bits) to linear form before integrating the charge, etc. But this
>>>> should
>>>> be feasible.
>>>> Asking for only a factor of 20 in dynamic range sounds low, but
>>>> I'll
>>>> wait to hear details at the meeting...
>>>>
>>>> Gerard
>>>>
>>>> Curtis A. Meyer wrote:
>>>>> Hi Everyone -
>>>>>
>>>>> there will be a combined tracking meeting on Monday July 28 at
>>>>> 1:30pm. I have created the Wiki page and put a couple of items
>>>>> on the agenda. Please add appropriate items as people see
>>>>> fit.
>>>>>
>>>>> - Curtis
>>>
>>>
>>> --
>>> Professor Curtis A. Meyer Department of Physics
>>> Phone: (412) 268-2745 Carnegie Mellon University
>>> Fax: (412) 681-0648 Pittsburgh PA 15213-3890
>>> cmeyer@ernest.phys.cmu.edu http://www.curtismeyer.com/
>>>
>>
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