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Re: first chips arriving
Hall D Electronics:
Hi Elke,
To add to the information in my reply to Elton today I would like to add
the following, which I realise still doesn't answer all your questions yet:
Re: first chips arriving
First off - money should still be reserved for a second prototype run at
MOSIS since there could be one on Nov 5, 2007 (or mid Feb 2008 for the next
possible date). This is primarily to produce a version that has a gain of
five for the FDC cathodes (for lower noise) and a selectable discriminator
for the FDC anodes (thus saving the cost of an external discriminator).
Secondarily, this run would allow addition of some sort of on-chip
calibration circuit and the opportunity to tweak the original design if
necessary. This second run would likely cost $ 27,331 USD for the MOSIS
production. Mitch Newcomer will also need funding to cover the following
time spent on the design leading up to the submission:
Estimated time - 1. Selectable gain of five - Two weeks
2. Selectable discriminator – 1-2 months
3. Tweak original design - ? (1 month?)
4. Calibration circuit- ? (1 month?)
Secondly – the prototype testing and full scale production testing should be
considered completely separate except for the fact that experience with the
prototype testing, including the chamber tests, will help point to the tests
we might want to do for the full production.
The motivation for the testing of the first ten to fifteen ASICs is to see
if they are functional enough to warrant mounting on preamp circuit boards
so that they can be tested as soon as possible on the small scale FDC
prototype or CDC prototype. We would basically be looking for any chips or
channels which behave abnormally with regard to power draw, gain, rise time,
pulse shape, noise levels, dc levels and cross talk. The chamber tests may
point to other tests which can be done on the remaining ASICs which might
take a little longer.
I hope this helps so far.
John
> Hall D Electronics:
>
> Dear John and Lars,
>
> as the chips of mosis will soon arrive, and the plan is to test them in
> Alberta, what exactly is planned.
>
> There are a couple of thisgs to be discussed about this.
> First of all what is the status of the test stand, what tests are planned,
> I'm sure Mitch and Fernando, have quite some ideas.
> What is the time line for the test, so when can we expect tested chips for
> the chamber front end cards.
>
> Than I have money reserved for a second run at mosis in fy07, do we need
> this money or can I use it for some other R&D. Is the plan that the
> testing of the final chips is also done in alberta, which would be a
> senseful slution if now time is invested to setup a test stand in alberta.
>
> I think I would really like to see a clear plan for the project, so that
> we all know what to expect of whom when ain which time, that makes it also
> easier to set up contracts in time.
>
> Thanks for the information and cooperation
> elke
>
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John Schaapman Ph: 780-492-3043
Centre for Particle Physics Fax: 780-492-3408
CEB-158
Mailstop #615
University of Alberta
Edmonton, AB
CANADA T6G 2G7