Re: P0 connector, busy questions

[Chris Cuevas <cuevas@jlab.org>]

Hall D Electronics:

Hi,

Definitely plan on using LVDS for the busy.  We are moving forward with
the design for the "B" switch module and ordering more of the FADC-250
prototypes to begin testing with multiple boards in a crate.  The "B"
switch will 'collect' these busy signals and will have the capability of
masking any boards producing busy problems.

You have definitely explained the critical timing concerns for the
trig/sync including the setup/hold windows especially at 250MHz.  Plenty
of tests to perform once we finish the Trigger Interface and "B" switch
modules.

Again, using P2 for signals will be useful for testing and development.
Remember the press fit P0 will bump into the 2mm-J0 connector on most 64x
crates, so during initial testing you may want to omit the P0 connector
from the board assembly.

Electronically,
Chris




On Thu, 6 Mar 2008, Gerard Visser wrote:

> Hi Fernando,
> 	Well, I'm not sure what you mean if you're saying that the trigger bits
> (for instance TRIG, SYNC, SPARE) are not time critical, these _are_ to
> be received synchronously on the front end boards. At least this is my
> understanding.
> 	For the ADC125 it is not a big deal, with typical setup/hold window of
> 2 ns (using FPGA IOB) I still have 6 ns left to play with. A ns or two
> of drift is not a big deal, if the (mean) phase is correct. For the
> FADC250, you have maybe 2-3 ns, losing 1 more ns from drift is not
> something to take lightly, I would think.
> 	[Yes setup/hold window can be reduced to 200 ps or less if external
> flip-flops are used instead of FPGA IOB's. I'm not planning it, anyway
> for 125MHz clock this would be overkill. For 250MHz it's not crazy.]
> 	Yes I concur, we will use VXS for the ADC125 in HallD. (This raises the
> cost of the board by about $60, not too bad.) I will also put the P2
> option on though, as originally planned, so that users of the maodule
> (including myself) do not have to have a VXS crate.
> 	I will use "universal" receivers as mentioned, so the clock and
> trigger/command lines can be driven by the VXS clock/timing "switch"
> using LVDS, PECL, or any other differential standard within the 0-3.3V
> range.
> 	I don't think I'm hearing in your email a definitive ruling whether to
> use single-ended open-drain or LVDS for the BUSY output on P0. I don't
> see the point to using LVDS for this, but if you guys wish it I will do
> so. Please give me a definitive ruling. On P2 the busy remains
> open-drain so it can be wire-or'd at the crate level. Busy is maskable
> so that problem boards can be debugged or worked around.
> 	Thanks,
>
> 	Gerard
>
> Fernando J. Barbosa wrote:
> > Hi Gerard,
> >
> > Sorry for the delay in answering your questions but I have been in a
> > review for a project in accelerator.
> >
> > I am getting Ed in the loop because he is the most appropriate person to
> > answer some of the questions you pose regarding the busy and the trigger
> > signals.
> >
> > With regards to using LVDS, yes you need to chose parts carefully as
> > specs change from manufacturer-to-manufacturer. However, these LVDS
> > signals are not critical for timing or synch as long as the time budgets
> > are considered for the various factors. For non-cw signals, I would stay
> > away from PECL, and probably CML, if signals need to go out of the
> > board. NECL is fine, though.
> >
> > At our last collaboration, we also decided on standardizing on VXS for
> > signal distribution. Therefore, there won't be any piggy-back
> > implementations. However, it is ok to put these signals on P2 for
> > testing and prototyping without the VXS features.
> >
> > Regards,
> > Fernando
> >
> >
> >
> >
> > Gerard Visser wrote:
> >> Hi Chris, Fernando,
> >>   Ok I can do that, I mean put busy out as LVDS on DP29+/-. Are you
> >> _sure_ you want to do that in LVDS? It is (for my module) an
> >> asynchronous busy, I will assert it when the module is getting close
> >> to full of triggers that it can handle, i.e., busy is the AF of the
> >> trigger FIFO. It will probably be sychronized to CLK but I won't
> >> guarantee that nor any particular timing relationship if I do
> >> synchronize to CLK. I would not expect the trigger system to receive
> >> busy synchronously nor to act on it "instantly" i.e. not in the next
> >> CLK cycle, I intend only that when busy is raised the trigger system
> >> should hold off following triggers within some reasonable time (few
> >> 100 ns) until it sees busy released again.
> >>   Is this the same model of busy you guys have for the FADC250?
> >>   In any case, I can put it as LVDS on DP29+/- or as open-drain on SE7
> >> or SE8, please write back with a final ruling.
> >>   I will leave busy as an open-drain output on the P2 connector, my
> >> thinking there is that a piggy-back backplane _can_ be constructed for
> >> P2, and if so then the crate busy will want to be a simple wire-or
> >> connection. If the hub architecture is employed instead, well it
> >> really doesn't matter whether the signal is LVDS or open-drain (with
> >> my timing model above).
> >>   On a separate issue, but also relevant for the clock/trigger
> >> distribution module, I will receive the clock and the three trigger
> >> bits (I call them TRG0,1,2, on the FADC250 they are called
> >> TRG,SYNC,SPARE_IN) each with an identical receiver device that can
> >> handle LVDS,LVPECL, or CML. I would urge you to strongly consider
> >> sending the trigger bits with the same driver type and signalling
> >> standard as the clock. Especially in the case of the FADC250, the
> >> period is only 4 ns and you could easily eat up 50% of the available
> >> timing budget by temperature or supply voltage delay differences
> >> between brand X LVDS driver and brand Y PECL driver. Anyway, the
> >> ADC125 will be compatible with any of the differential signal
> >> standards or any mixture of them - but I think it will be easiest to
> >> guarantee the TRG bit timing if you don't mix them.
> >>   Whether the three trigger bits encode 3, 8, 64, or whatever possible
> >> number of trigger commands (such as sync, trigger, raw-read-trigger,
> >> fire-pulser, reset, or whatever) is just a matter of FPGA code and we
> >> can discuss it later.
> >>   Thanks,
> >>
> >>     Gerard
> >>
> >> Chris Cuevas wrote:
> >>> Gerard,
> >>>
> >>> The FADC-250 parts list shows #1410147-1 as a Tyco part number for P0.
> >>>
> >>> As for the 'busy' signal to the B switch board please use DP29+/- (A15;
> >>> B15).  These are presently defined as LVDS_Status_Out and at our last
> >>> FADC/Trigger meeting on Friday we have come to 'final' agreement on the
> >>> signal definitions for the Trigger Interface slot (PP18) and of
> >>> course the
> >>> signal definitions for bot the Energy Sum Module(Switch-A) and
> >>> Clock_Trigger Distribution Module(Switch-B). I think your plan to
> >>> implement the capability to receive/send the clock/trig/busy signals
> >>> to P2
> >>> is a good idea.
> >>>
> >>>
> >>> The documentation for the
> >>> overall trigger, clock, and network system layout is progressing and the
> >>> drafts will be ready soon.  The VITA 41 documents certainly defined the
> >>> pair assignments, but for our crate system we need a two page table that
> >>> shows the signal names from each PayloadPort to each switch slot.
> >>> Designs
> >>> for the Trigger Interface module, full crate energy sum module and
> >>> ClockTrigger distribution module are a work in progress, so we will
> >>> finalize the signal assignments very soon.
> >>>
> >>> Regards,
> >>> Chris
> >>> ~~~~~~~~~~~~~~~~~~~~~~~
> >>>
> >>>
> >>> On Tue, 4 Mar 2008, Gerard Visser wrote:
> >>>
> >>>> Hall D Electronics:
> >>>>
> >>>> Hi Fernando,
> >>>>       Please confirm, the P0 connector is supposed to be AMP #
> >>>> 1410147-2,
> >>>> right? I don't have a copy of the VXS specifications document yet, I
> >>>> deduced this from AMP's webpage and some other docs I found on the web.
> >>>>       Also, I am thinking that I should send the ADC125 busy output
> >>>> on either
> >>>> G13(SE7) or G15(SE8) as an open-drain output. Can you confirm, these
> >>>> lines go on the backplane to the correct switch slot, the same one as
> >>>> the TRG,CLK lines you have chosen for FADC250? I suppose if the FAD250
> >>>> implements a busy out it will be LVDS on the LVDS_STATUS1_OUT_P0 line
> >>>> and it's complement, right?
> >>>>       I'm trying to finish off the P0 connections on the ADC125
> >>>> schematic,
> >>>> I'll look forward to hearing from you on this. Thanks,
> >>>>
> >>>>       Gerard
> >>>>
> >>>> p.s. Executive summary for the rest of you, ADC125 will take clock and
> >>>> trigger from, and send busy to, either P2 or P0/VXS,
> >>>> software-selectable. This also means I won't require a VXS crate for
> >>>> testing, except of course just to test the P0/VXS connections will
> >>>> require a VXS crate and suitable trigger/clock "switch" card. The
> >>>> trigger/clock "switch" card design will presumably be one design that
> >>>> can work with ADC125 or FADC250.
> >>>>
>