Re: P0 connector, busy questions

[Gerard Visser <gvisser@indiana.edu>]

Hall D Electronics:

Hi Chris,
	Ok, confirmed. Busy to P0 is LVDS. Of course I forgot to ask it 
earlier, but the polarity I assume is as follows. The module is BUSY if 
DP29+ is more positive than DP29-, otherwise NOT BUSY. If this should be 
flipped please tell me soon (it will be hardwired on the board, the same 
line driving the LVDS driver and the open-drain driver for P2 BUSY, 
which has of course a defined sense (BUSY=LOW) so it could be wire-or'd.
	The ADC125 will expect the TRG bits to change synchronously to (rising 
or falling) clock edge (you decide) and will be captured on the (falling 
or rising) edge. I assume that (one of these two plans) is what you have 
in mind for the "switch" card to provide.
	Thanks for the pointer about omitting the VXS connector, I hadn't 
noticed that issue but I see it now. I will leave it off, that also 
saves me begging/borrowing/stealing some connectors.

	Gerard

Chris Cuevas wrote:
> Hi,
> 
> Definitely plan on using LVDS for the busy.  We are moving forward with
> the design for the "B" switch module and ordering more of the FADC-250
> prototypes to begin testing with multiple boards in a crate.  The "B"
> switch will 'collect' these busy signals and will have the capability of
> masking any boards producing busy problems.
> 
> You have definitely explained the critical timing concerns for the
> trig/sync including the setup/hold windows especially at 250MHz.  Plenty
> of tests to perform once we finish the Trigger Interface and "B" switch
> modules.
> 
> Again, using P2 for signals will be useful for testing and development.
> Remember the press fit P0 will bump into the 2mm-J0 connector on most 64x
> crates, so during initial testing you may want to omit the P0 connector
> from the board assembly.
> 
> Electronically,
> Chris