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Re: fADC stop pointer
Yves,
Sounds like you have a situation where the relative timing of the signal
and trigger pulses is sitting on some timing/clock-division boundary. To
test this you can add a small delay (say 20% of the least time count = 1
ns or so) in the signal or the trigger and see if the behavior changes
(i. e., becomes stable).
If this is the "problem" then I'd say it is really a "feature".
-- Mark
Yves Van Haarlem wrote:
> Hall D Electronics:
>
> Hi All,
>
> I did a test concerning fADC timing, it is described in:
>
> http://www.jlab.org/Hall-D/software/wiki/index.php/FADC_timing
>
> In short: it turns out that the stop pointer returned by the fADC
> jumps around (~20ns or 4 bins) - I believe this should not be the
> case. This test was performed using the internal clock in the fADC - I
> will repeat this test with the external clock. This behavior is
> confirmed by Gregg Franklin an Diana Parno who use the same fADC with
> different readout software for the Hall-A polarimeter upgrade (they
> saw a cut-off at the end and I saw the rising edge moving -- see
> description on the website).
>
>
> Cheers,
> Yves
>
>
>
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