fADC timing -- solution found

[Yves Van Haarlem <yvhaarle@ernest.phys.cmu.edu>]

Hall D Electronics:

Hi Mark,

Thank you for your suggestion.

By reading the manual of the fADC, especially the part concerning event 
directories, I found a solution. This page tells you that if you have an 
event directory with the trigger bit set then the last 25 bits of that 
data word contain the pointer to the next sample address (or the start of 
your event - i call this start pointer). So far so good - this is what i 
use in my code.

The end of that section reads: for more information .... see Next Sample 
Address: this extra info (5 pages back) tells you that the first two bits 
of the next sample address (bit 0 and 1) contain extra information - they 
tell you how much the start pointer is off...:

bit0  bit1   meaning
0     0      all OK 
0     1      1 sample before stop is not stored + correct start-pointer +1
1     0      2 samples before stop not stored + correct start-pointer +2
1     1      1 sample after stop stored + correct start-pointer -1

If you apply these corrections you see that eg in case 0 1 that your 
leading edge is at the correct time but you have a cut off in the last 
sample (last sample is not stored). In case 1 1 you see a signal in first 
sample => that is the sample after the stop that is stored. I hope it 
makes sense. Otherwise -> read the manual.

Cheers,
 	Yves

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On Thu, 3 Apr 2008, Mark M. Ito wrote:

> Yves,
>
> Sounds like you have a situation where the relative timing of the signal and 
> trigger pulses is sitting on some timing/clock-division boundary. To test 
> this you can add a small delay (say 20% of the least time count = 1 ns or so) 
> in the signal or the trigger and see if the behavior changes (i. e., becomes 
> stable).
>
> If this is the "problem" then I'd say it is really a "feature".
>
> -- Mark
>
> Yves Van Haarlem wrote:
>> Hall D Electronics:
>> 
>> Hi All,
>> 
>> I did a test concerning fADC timing, it is described in:
>> 
>> http://www.jlab.org/Hall-D/software/wiki/index.php/FADC_timing
>> 
>> In short: it turns out that the stop pointer returned by the fADC jumps 
>> around (~20ns or 4 bins) - I believe this should not be the case. This test 
>> was performed using the internal clock in the fADC - I will repeat this 
>> test with the external clock. This behavior is confirmed by Gregg Franklin 
>> an Diana Parno who use the same fADC with different readout software for 
>> the Hall-A polarimeter upgrade (they saw a cut-off at the end and I saw the 
>> rising edge moving -- see description on the website).
>> 
>> 
>> Cheers,
>>     Yves
>> 
>> 
>>
>>                           /--------------------------------
>>                          /   Yves Van Haarlem
>>        _--~~--_         /
>>      /~/_|  |_\~\      /      Carnegie Mellon University
>>     |____________|    /        Department of Physics
>>     |[][][][][][]|:= /          Wean Hall room 8404
>>   __| __         |__ \            Pittsburgh, PA 15213
>>  |  ||. |   ==   |  | \           USA
>> (|  ||__|   ==   |  |) \
>>  |  |[] []  ==   |  |   \           Tel.:   +1 412 268-6949
>>  |  |____________|  |    \                  +1 412 641-9252
>>  /__\            /__\     \          Fax.: +1 412 681-0648
>>   ~~              ~~       \-----------------------------------
>