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Re: FEU84-3 / FADC Timing



Hi Matt and Mihajlo,

The results are indeed impressive! These also point to the stability of 
the ADC.

I don't understand what you mean by the +/- 4 ns noise. Do you mean 
missing samples on the leading edge? In order to get the full resolution 
from a 10-bit ADC running at 250 MSPS, the clock must be stable to less 
than 2 ps (jitter). For 12-bit ADCs running at the same 250 MSPS, the 
clock must be stable to less than 350 fs! For the energy sum, these 
numbers can be considerably relaxed but for timing from the fADC, we 
need to measure the timing resolution dependence on clock stability. 
This would be a very interesting measurement that could be checked by 
modulating the clock signal. In any case, we have tested clock 
distribution circuits with optical fibers to be stable to better than 2 
ps and that's our present plan.

I completely agree that there are quite a few tests left regarding the 
timing stability. The PMT & CW stability tests will provide a measure as 
to what level of control we need to have over the voltage setting, 
temperature, etc. The temperature in the hall is expected to be stable 
around 70 F but the characteristics of the cable must be well understood 
so that temperature does not become a factor. Eventually, I think it 
would also be useful to characterize the timing algorithm for single 
shot resolution and if it changes over time, perhaps in combination with 
a high resolution TDC. The F1TDC has a resolution of 60 ps if needed.

I look forward to your presentations next week during the collaboration 
meeting. It may also be a good time to start discussing the algorithm 
implementation on a FPGA.

Thanks and regards,
Fernando



Matthew Shepherd wrote:
>
> Hi Fernando,
>
> Mihajlo has been making nice progress with a single FADC card.  We do 
> this by dividing the pulse and send one copy into the card.  The other 
> part we bounce off the end of the long cable and also send it into the 
> card.  This leaves then two copies of the same pulse in a single 
> readout buffer of the FADC.  We can shift the clock phase between the 
> samples by varying the length of the cable used to generate the 
> reflection.  We apply the time measurement algorithm to both pulses 
> and look at the RMS of the difference between the pulses over many 
> events (the mean of the difference gives the delay).  For large pulses 
> (near full scale on the 8 bit FADC) we are see typical RMS differences 
> of order 150 ps or single channel timing resolutions around 100 ps.  
> It is impressive (suprising?) that the timing resolution is this 
> good.  We are also investigating dependence on pulse height.
>
> One conclusion is already evident:  the synchronized clock for all 
> readout channels is absolutely essential.  If we would had some +- 4 
> ns noise on top of this it would completely wash out the sharp timing 
> resolution we can get with the PMT FADC system.
>
> I think we also need to explore absolute time stability of a single 
> tube.  The cable lengths will certainly stay fixed, but changing the 
> voltage may shift the absolute transit time within in a tube at the 
> level that we are sensitive to in our calibrations.
>
> We look forward to hearing your input and plan to present some results 
> at the collaboration meeting next week.
>
> -Matt
>
>
> On Apr 15, 2008, at 7:45 AM, Fernando J. Barbosa wrote:
>> Hi Matt,
>>
>> We have clock distribution boards that output multiple (five) NIM 
>> replicas and were designed for providing synchronized clocks to 
>> multiple fADCs on a small setup. These were recently designed by 
>> Gerard and Kim and are available with 250 MHz clocks. These sources 
>> include the power supply.
>>
>> If these are of interest to you, we can ship you one now.
>>
>> Regards,
>> Fernando
>